Scipediacontent: Scipediacontent moved page Draft Content 610573679 to Traber et al 2015a

2021-02-08T09:14:54Z

Scipediacontent moved page Draft Content 610573679 to Traber et al 2015a

Scipediacontent: Created page with " == Abstract == Baseline RISC instruction sets for ultra-low power processors are constantly being tuned to reduce cycle count when executing computation-intensive applicatio..."

2021-02-08T09:14:52Z

Created page with " == Abstract == Baseline RISC instruction sets for ultra-low power processors are constantly being tuned to reduce cycle count when executing computation-intensive applicatio..."

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== Abstract ==

Baseline RISC instruction sets for ultra-low power processors are constantly being tuned to reduce cycle count when executing computation-intensive applications. Performance improvements often come at a non-negligible price in terms of area and critical path length and imply deeper pipelines and complex memory interfaces. This penalizes control-intensive code execution and significantly increases cost and complexity of building multi-core clusters. In addition, some extensions are not easily exploited by compilers and may increase code development effort, especially when considering parallel applications. In this paper we describe our efforts in enhancing a baseline open ISA (OpenRISC) and its LLVM compiler back-end to significantly reduce execution cycles while minimizing the impact on core micro-architecture complexity, number of pipeline stages, area and power. In addition, we improved the core micro-architecture to streamline its integration in a tightly-coupled cluster, sharing instruction cache and data memory, thereby further enhancing parallel execution efficiency. The combined effect of ISA, compiler and micro-architecture evolution gives an average energy efficiency boost of 59% on vector intensive code and 41% otherwise, at an area and power increase of 2.3% and 18% on a four-core processor cluster.

== Original document ==

The different versions of the original document can be found in:

* [http://hdl.handle.net/11585/545775 http://hdl.handle.net/11585/545775]

* [http://xplorestaging.ieee.org/ielx7/7304349/7314373/07314386.pdf?arnumber=7314386 http://xplorestaging.ieee.org/ielx7/7304349/7314373/07314386.pdf?arnumber=7314386],
: [http://dx.doi.org/10.1109/vlsi-soc.2015.7314386 http://dx.doi.org/10.1109/vlsi-soc.2015.7314386]

* [https://ieeexplore.ieee.org/document/7314386 https://ieeexplore.ieee.org/document/7314386],
: [https://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2015.html#GautschiTPBSFBA15 https://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2015.html#GautschiTPBSFBA15],
: [http://dx.doi.org/10.1109/VLSI-SoC.2015.7314386 http://dx.doi.org/10.1109/VLSI-SoC.2015.7314386],
: [https://doi.org/10.1109/VLSI-SoC.2015.7314386 https://doi.org/10.1109/VLSI-SoC.2015.7314386],
: [http://ieeexplore.ieee.org/document/7314386 http://ieeexplore.ieee.org/document/7314386],
: [https://academic.microsoft.com/#/detail/1905460592 https://academic.microsoft.com/#/detail/1905460592]

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Traber et al 2015a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 610573679 to Traber et al 2015a

Scipediacontent: Created page with " == Abstract == Baseline RISC instruction sets for ultra-low power processors are constantly being tuned to reduce cycle count when executing computation-intensive applicatio..."