Scipediacontent: Scipediacontent moved page Draft Content 344062031 to Mok et al 2017a

2021-01-28T16:37:55Z

Scipediacontent moved page Draft Content 344062031 to Mok et al 2017a

Scipediacontent: Created page with " == Abstract == This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Ins..."

2021-01-28T16:37:52Z

Created page with " == Abstract == This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Ins..."

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== Abstract ==

This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Instruction Set Architecture) compatible 5-stage pipeline processor, RISC32. Our work can be used as a reference for RISC32 processor developers to identify and resolve every possible data hazard that might arise during execution phase within the range of the basic MIPS core instruction set. The techniques used to resolve data hazard in this paper are data forwarding and pipeline stages stalling. When data hazard arises, it is first resolve by using data forwarding. If the problem persists, we use pipeline stages stalling then only follow by another data forwarding to resolve the data hazard. This combination will reduce the impact of data hazard on the processor throughput, instead of only using the pipeline stages stalling. This paper delivers a comprehensive analysis and the development of the data hazard resolving blocks that are able to resolve data hazard arises.

== Original document ==

The different versions of the original document can be found in:

* [http://dx.doi.org/10.1109/waina.2017.20 http://dx.doi.org/10.1109/waina.2017.20]

* [https://strathprints.strath.ac.uk/61831/1/Kiat_etal_IEEE_WAINA_2017_A_comprehensive_analysis_on_data_hazard_for_RISC32_5_Stage.pdf https://strathprints.strath.ac.uk/61831/1/Kiat_etal_IEEE_WAINA_2017_A_comprehensive_analysis_on_data_hazard_for_RISC32_5_Stage.pdf]

* [http://xplorestaging.ieee.org/ielx7/7929133/7929495/07929670.pdf?arnumber=7929670 http://xplorestaging.ieee.org/ielx7/7929133/7929495/07929670.pdf?arnumber=7929670],
: [http://dx.doi.org/10.1109/waina.2017.20 http://dx.doi.org/10.1109/waina.2017.20]

* [https://dblp.uni-trier.de/db/conf/aina/ainaw2017.html#KiatMLGA17 https://dblp.uni-trier.de/db/conf/aina/ainaw2017.html#KiatMLGA17],
: [https://strathprints.strath.ac.uk/61831 https://strathprints.strath.ac.uk/61831],
: [https://pureportal.strath.ac.uk/en/publications/a-comprehensive-analysis-on-data-hazard-for-risc32-5-stage-pipeli https://pureportal.strath.ac.uk/en/publications/a-comprehensive-analysis-on-data-hazard-for-risc32-5-stage-pipeli],
: [https://academic.microsoft.com/#/detail/2616201477 https://academic.microsoft.com/#/detail/2616201477]

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Mok et al 2017a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 344062031 to Mok et al 2017a

Scipediacontent: Created page with " == Abstract == This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Ins..."