Jaaskelainen et al 2007a - Revision history

Scipediacontent at 13:36, 21 January 2021

2021-01-21T13:36:17Z

Scipediacontent: Scipediacontent moved page Draft Content 587951443 to Jaaskelainen et al 2007a

2020-09-29T07:59:35Z

Scipediacontent moved page Draft Content 587951443 to Jaaskelainen et al 2007a

Scipediacontent: Created page with " == Abstract == Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors...."

2020-09-29T07:59:33Z

Created page with " == Abstract == Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors...."

New page

== Abstract ==

Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed. This paper evaluates several resource conflict detection models, commonly used in compiler instruction scheduling, in the context of function unit pipeline simulation. The evaluated models include the conventional reservation table based-model, the dynamic collision matrix model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides comparable simulation speed to the actively initialized FSA.

Document type: Part of book or chapter of book

== Full document ==
<pdf>Media:Draft_Content_587951443-beopen11731-6430-document.pdf</pdf>

== Original document ==

The different versions of the original document can be found in:

* [http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf]

* [http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25 http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25],[http://dx.doi.org/10.1007/978-3-540-73625-7_25 http://dx.doi.org/10.1007/978-3-540-73625-7_25]

* [https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml],[https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/plain https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/plain],[http://dx.doi.org/10.1016/j.sysarc.2008.04.002 http://dx.doi.org/10.1016/j.sysarc.2008.04.002] under the license https://www.elsevier.com/tdm/userlicense/1.0/

* [https://link.springer.com/chapter/10.1007/978-3-540-73625-7_25 https://link.springer.com/chapter/10.1007/978-3-540-73625-7_25],[https://academic.microsoft.com/#/detail/2123220156 https://academic.microsoft.com/#/detail/2123220156]

* [https://www.sciencedirect.com/science/article/pii/S1383762108000593 https://www.sciencedirect.com/science/article/pii/S1383762108000593],[http://dblp.uni-trier.de/db/journals/jsa/jsa54.html#JaaskelainenGK08 http://dblp.uni-trier.de/db/journals/jsa/jsa54.html#JaaskelainenGK08],[https://academic.microsoft.com/#/detail/2079377457 https://academic.microsoft.com/#/detail/2079377457]

* [ ]

DOIS: 10.1016/j.sysarc.2008.04.002 10.1007/978-3-540-73625-7_25

@@ Line 3: / Line 3: @@
 Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed. This paper evaluates several resource conflict detection models, commonly used in compiler instruction scheduling, in the context of function unit pipeline simulation. The evaluated models include the conventional reservation table based-model, the dynamic collision matrix model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides comparable simulation speed to the actively initialized FSA.
@@ Line 16: / Line 11: @@
 * [http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf http://tce.cs.tut.fi/papers/FU_conflict_detection.pdf]
-* [http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25 http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25],[http://dx.doi.org/10.1007/978-3-540-73625-7_25 http://dx.doi.org/10.1007/978-3-540-73625-7_25]
+* [http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25 http://www.springerlink.com/index/pdf/10.1007/978-3-540-73625-7_25],
-* [https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml],[https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/plain https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/plain],[http://dx.doi.org/10.1016/j.sysarc.2008.04.002 http://dx.doi.org/10.1016/j.sysarc.2008.04.002] under the license https://www.elsevier.com/tdm/userlicense/1.0/
+* [https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml https://api.elsevier.com/content/article/PII:S1383762108000593?httpAccept=text/xml],
-* [https://link.springer.com/chapter/10.1007/978-3-540-73625-7_25 https://link.springer.com/chapter/10.1007/978-3-540-73625-7_25],[https://academic.microsoft.com/#/detail/2123220156 https://academic.microsoft.com/#/detail/2123220156]
+* [https://dblp.uni-trier.de/db/journals/jsa/jsa54.html#JaaskelainenGK08 https://dblp.uni-trier.de/db/journals/jsa/jsa54.html#JaaskelainenGK08],
-* [https://www.sciencedirect.com/science/article/pii/S1383762108000593 https://www.sciencedirect.com/science/article/pii/S1383762108000593],[http://dblp.uni-trier.de/db/journals/jsa/jsa54.html#JaaskelainenGK08 http://dblp.uni-trier.de/db/journals/jsa/jsa54.html#JaaskelainenGK08],[https://academic.microsoft.com/#/detail/2079377457 https://academic.microsoft.com/#/detail/2079377457]
+* [https://link.springer.com/chapter/10.1007/978-3-540-73625-7_25 https://link.springer.com/chapter/10.1007/978-3-540-73625-7_25],
 * [ ]

← Older revision	Revision as of 07:59, 29 September 2020
(No difference)