Scipediacontent at 14:35, 21 January 2021

2021-01-21T14:35:44Z

Scipediacontent: Scipediacontent moved page Draft Content 747470330 to Grigore et al 2018a

2020-10-14T13:30:51Z

Scipediacontent moved page Draft Content 747470330 to Grigore et al 2018a

Scipediacontent: Created page with " == Abstract == Making full use of the capabilities of the FPGA as an accelerator is difficult for non hardware experts, especially if partial reconfiguration is to be employ..."

2020-10-14T13:30:48Z

Created page with " == Abstract == Making full use of the capabilities of the FPGA as an accelerator is difficult for non hardware experts, especially if partial reconfiguration is to be employ..."

New page

== Abstract ==

Making full use of the capabilities of the FPGA as an accelerator is difficult for non hardware experts, especially if partial reconfiguration is to be employed. One of the issues that arise is to physically implement modules into bounding boxes of minimum size for improving fragmentation cost and reconfiguration time. In this paper we present a method which automates the modules designing step, fulfilling module resource requirements and architectural FPGA constraints. We present a case study that shows how our automatic module implementation flow can be used to generate run-time reconfigurable bitstreams that are suited for stitching together processing pipelines directly from a Maxeler MaxJ HLS specification. This takes into consideration design alternatives, fragmentation, and routing failure mitigation strategies.

Document type: Part of book or chapter of book

== Full document ==
<pdf>Media:Draft_Content_747470330-beopen799-2433-document.pdf</pdf>

== Original document ==

The different versions of the original document can be found in:

* [http://dx.doi.org/10.1007/978-3-319-77610-1_20 http://dx.doi.org/10.1007/978-3-319-77610-1_20] under the license http://www.springer.com/tdm

* [https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf]

DOIS: 10.1007/978-3-319-77610-1 10.1007/978-3-319-77610-1_20

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 Making full use of the capabilities of the FPGA as an accelerator is difficult for non hardware experts, especially if partial reconfiguration is to be employed. One of the issues that arise is to physically implement modules into bounding boxes of minimum size for improving fragmentation cost and reconfiguration time. In this paper we present a method which automates the modules designing step, fulfilling module resource requirements and architectural FPGA constraints. We present a case study that shows how our automatic module implementation flow can be used to generate run-time reconfigurable bitstreams that are suited for stitching together processing pipelines directly from a Maxeler MaxJ HLS specification. This takes into consideration design alternatives, fragmentation, and routing failure mitigation strategies.
@@ Line 17: / Line 12: @@
 * [https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf https://www.research.manchester.ac.uk/portal/files/64823020/hls_enabled_partially.pdf]
-DOIS: 10.1007/978-3-319-77610-1 10.1007/978-3-319-77610-1_20
+DOIS: 10.1007/978-3-319-77610-1_20 10.1007/978-3-319-77610-1

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Grigore et al 2018a - Revision history

Scipediacontent at 14:35, 21 January 2021

Scipediacontent: Scipediacontent moved page Draft Content 747470330 to Grigore et al 2018a

Scipediacontent: Created page with " == Abstract == Making full use of the capabilities of the FPGA as an accelerator is difficult for non hardware experts, especially if partial reconfiguration is to be employ..."