http://www.colloquiam.com/wd/index.php?action=history&feed=atom&title=Alvarez-Farre_et_al_2021aAlvarez-Farre et al 2021a - Revision history2026-05-17T06:21:34ZRevision history for this page on the wikiMediaWiki 1.27.0-wmf.10http://www.colloquiam.com/wd/index.php?title=Alvarez-Farre_et_al_2021a&diff=219920&oldid=prevScipediacontent: Scipediacontent moved page Draft Content 721176048 to Alvarez-Farre et al 2021a2021-03-11T16:39:47Z<p>Scipediacontent moved page <a href="/public/Draft_Content_721176048" class="mw-redirect" title="Draft Content 721176048">Draft Content 721176048</a> to <a href="/public/Alvarez-Farre_et_al_2021a" title="Alvarez-Farre et al 2021a">Alvarez-Farre et al 2021a</a></p>
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<td colspan='1' style="background-color: white; color:black; text-align: center;">Revision as of 16:39, 11 March 2021</td>
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</td></tr></table>Scipediacontenthttp://www.colloquiam.com/wd/index.php?title=Alvarez-Farre_et_al_2021a&diff=219919&oldid=prevScipediacontent: Created page with "== Abstract == The sparse matrix-vector product is a widespread operation amongst the scientific computing community. It represents the dominant computational cost in many la..."2021-03-11T16:39:44Z<p>Created page with "== Abstract == The sparse matrix-vector product is a widespread operation amongst the scientific computing community. It represents the dominant computational cost in many la..."</p>
<p><b>New page</b></p><div>== Abstract ==<br />
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The sparse matrix-vector product is a widespread operation amongst the scientific computing community. It represents the dominant computational cost in many large-scale simulations relying on iterative methods, and its performance is sensitive to the sparse pattern, the storage format and kernel implementation, and the target computing architecture. In this work, we are devoted to the efficient execution of the sparse matrix-vector product on (potentially hybrid) modern supercomputers with non-uniform memory access configurations. A hierarchical parallel implementation is proposed to minimise the number of processes participating in distributed-memory parallelisation. As a result, a single process per computing node is enough to engage all its hardware and ensure efficient memory access on manycore platforms. The benefits of this approach have been demonstrated on up to 9,600 cores of MareNostrum 4 supercomputer, at Barcelona Supercomputing Center.<br />
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== Full document ==<br />
<pdf>Media:Draft_Content_721176048p5653.pdf</pdf></div>Scipediacontent